This invention relates to a logical circuit comprising a plurality of transistors connected in series for use in an NAND circuit, an NOR circuit, or the like having a plurality of inputs and, in particular, to a semiconductor integrated circuit arrangement for integrating the logical circuit by the use of a semiconductor.
As an N-input NAND circuit constituted by the use of MOS (metal oxide semiconductor) transistors as MIS (metal insulator semiconductor) transistors, a logical circuit is known which has a logical unit including n-channel MOS transistors, N in number, connected in series or cascade, where N represents an integer greater than one. As an N-input NOR circuit, another logical circuit is known which has another logical unit including p-channel MOS transistors, N in number, connected in series or cascade. In the above-mentioned logical circuits, it is desired to design the circuit so as to avoid occurrence of time lag of outputs for different inputs due to unbalance in input wires (including gates) and gate capacitance and junction capacitance appearing in the output.
A conventional logical circuit of the type is disclosed in Japanese Unexamined Patent Publication (JP-A) No. 202616/1967 (hereinafter called prior art).
In the prior art, a logical unit for switching operation in the NAND circuit (or the NOR circuit) comprises transistor arrays, N or N! in number, connected in parallel, each transistor array comprising n-channel MOS transistors (or p-channel MOS transistors), N in number, connected in series or cascade. The n-channel or the p-channel MOS transistors in the respective arrays are arranged so that their gates are connected in a cyclic fashion.
In the NAND or the NOR circuit of the prior art having the above-mentioned structure, difference in delay time of outputs for different inputs may be eliminated.
However, in the above-mentioned prior art, it is necessary to use a large number of transistors in the logical unit as the number N of the inputs increases. This increases the required art area and complicates the layout of interconnection between the transistors. For example, in case of five inputs (that is, N is equal to 5), the number of transistors used In the logical unit is as enormously large as 5.times.5 (=N.times.N) or 5!=5.times.4.times.3.times.2.times.1 (=N!).
The prior art shows electrical circuit diagrams alone. No description is provided about disadvantages in cases where the circuit shown in the prior art is practically implemented as an integrated circuit. Therefore, when the circuit exemplified in the prior art is straightforwardly integrated, the increase in area is inevitable following the increase in number of required devices.
It is noted here that the increase in area directly results in the increase in chip area. This is a bar against downsizing of a chip. In addition, the increase in number of the devices makes the layout of interconnection lengthy and complicated. This often results in an inbalance in the interconnections.